Low power design considerations using CMOS FDSOI for LTE front ends

Author: 
Platt, D.
Type of publication: 
Conference item
Abstract: 

A conference presentation introduces the Catrene  Dynamic-ULP project (CT210). A discussion concerning the potential advantages of the ST Microelectronics 28nm CMOS FDSOI Technology compared to the equivalent 28nm bulk CMOS technology node is made, in particular by performing a theoretical comparison of an equivalent broadband LNA design using 28nm CMOS FDSOI, 28nm bulk CMOS and 65nm CMOS PDSOI. Finally the 28nm CMOS FDSOI technology is considered with respect to low power and low noise circuit design applicable to LTE mobile device front-ends.

Year: 
2013
Official URL: 
https://www.edacentrum.de/en/edaworkshop/program
Published in: 
edaWorkshop13/Catrene DTC