ProjectPlaces2BE

Competence Areas at RISE ICT
Places2BE

Pilot Line for Advanced CMOS Enhanced by SOI in 2x nodes, Built in Europe

Project Description

Places2BE is a Key Enabling Technology (KET) project. The general objective of the complete PLACES2BE project is the industrialization of 28nm and 14nm Fully Depleted Silicon On Insulator (FDSOI) Technology platforms, enabling two different sources in two different European countries (Germany - Global Foundries and France - STMicroelectronics). The project also aims at establishing and reinforcing a design ecosystem in Europe using these platforms. Finally, the project considers it extremely important to explore further down-scaling towards FDSOI devices at 10nm, in order to continue the road towards even more efficient nano-scale CMOS technologies.

Within the PLACES2BE project, Acreo will contribute to the industrialization of 28nm and 14nm FDSOI CMOS technology by helping to establish and by participating in the European design ecosystem around CMOS FDSOI.  Acreo will focus on FDSOI IP development for high frequency power and power switching components for next-generation wireless LTE transceivers and other emerging communications applications.The project builds upon Acreo’s experience with SOI design for high frequency applications within the SIAM project and the Dynamic-ULP project and will be performed in close collaboration with Ericsson Research in Lund and ST Ericsson.

Acreo will participate on two FDSOI wafer shuttles to implement the IP blocks and test circuits designed in order to verify electrical and thermal performance. The circuits designed will look to apply the potential advantages that are offered by the CMOS FDSOI technology. A demonstrator test chip, compatible for test with LTE system test equipment simulating real mobile traffic transmission scenarios, will be designed and tested for compliance with the relevant LTE specifications. Careful characterization of the power consumption and thermal performance will be made.

Project Summary

Project Label: Pilot Line for Advanced CMOS Enhanced by SOI in 2x nodes, Built in Europe (ENIAC)
Project Acronym: Places2BE
Project Duration: 3 years starting January 2013
Project Coordinator: STMicroelectronics
Project Partners: STMicroelectonics, Ericsson Research, ST-Ericsson, CEA-LETI, SOITEC, Adixen Vacuum Products, Mentor Graphics, Ion Beam Services, Institut Polytechnique de Grenoble, Dolphin, Université Catholique de Louvain, IMEC, Global Foundries, Forschungzentrum Jülich, University of Twente, Axiom, Bruco Integrated Circuits, eSilicon, Acreo Swedish ICT
Project Funding (Swedish and European): Vinnova and ENIAC

For more information visit Vinnova