ProjectDynamic-ULP: Smaller, Faster, Better CMOS Technology

Competence Areas at RISE ICT
Dynamic-ULP: Smaller, Faster, Better CMOS Technology

The Dynamic-ULP (Ultra Low Power) project is a pan-European project to develop fully depleted silicon-on-insulator (FDSOI) CMOS technology with 20nm gate lengths. In Sweden, Acreo and ST-Ericsson will assess the new semiconductor technology for use in mobile phone transceiver ASICs.

FDSOI technology is being developed by the semiconductor industry to allow the continued shrinking of the transistor size according to Moore’s Schedule (also referred to as a Law). MOS transistor size reduction has caused variability and leakage current to become a serious problem for continued downscaling. By using an ultra-thin insulating layer between the silicon wafer and the transistor, the parasitic capacitance is reduced which allows for blazingly fast operation and low leakage currents (read less power consumption). In addition, due to the very tiny channel dimensions, under normal bias conditions, the channel where current flows through the transistor is fully-depleted of charge carriers. This makes for a more consistent transistor with less parameter variation when compared with the standard bulk CMOS transistor without an insulating layer.

In addition to the improved transistor properties, FDSOI devices also can be biased from the substrate or “back-side” therefore allowing the transistor to be dynamically tuned for the optimum trade-off between power consumption and performance depending on the operating mode of the application. This is important to reduce power-consumption and conserve battery time in a mobile phone or tablet.
While the 20nm FDSOI process is being developed in France by ST Microelectronics, in Sweden we will apply this technology for the mobile phone application. Acreo, together with ST-Ericsson in Lund, Sweden, will develop some of the worlds first circuit blocks for mobile phones using this technology.

The project is building upon Acreo’s experience with SOI design for high frequency applications within the SIAM project.

Project Summary

Project Objective: To develop circuits and systems on chip (SOC) for mobile phone applications using 20nm FDSOI CMOS technology.
Project Label: CT210 – DYNAMIC-ULP (Eureka)
Project Duration: 3 years starting January 2012
Project Leader: STMicroelectronics
Project Partners: STMicroelectronics, ST-Ericsson, Ericsson Microelectronics, SOITEC, Atrenta, Infiniscale, Dolphin, CEA-LETI, Acreo Swedish ICT
Project Funding (Swedish): Vinnova

For more information visit Vinnova