The thin film HDI substrate technology at Acreo is based on thin film deposition and high resolution lithography technologies.
THIN FILM PROCESSES
Metal deposition of the conductor layers is done using DC magnetron sputtering, which is a physical vapor deposition (PVD) method.
Patterning of the interconnect structure is performed by wet etching through a photo resist mask. The photo resist is deposited by spin coating, exposed through a chrome/glass mask, and developed.
The dielectric layer or insulator is deposited by spin coating. Using a photo-sensitive dielectric material, the patterning (e.g. to form vias) is done directly through a chrome/glass mask, and then developed.
In case of a non photosensitive dielectric material, the patterning is achieved by reactive ion etching (RIE), also named dry etching and plasma etching, through a metal mask deposited and patterned in the same way as the metal conductor layer. After RIE, the metal mask is etched away.
We are also able to deposit metals and various inorganic materials, using resistive or electron beam evaporation.
BUILD-UP MATERIALS
We normally use Cu or Al to make conductor lines and Ti as adhesion promoting layer, as well as diffusion barrier. Ni/Cr is used for integrated resistors, when needed.
As dielectric layer, we use mostly BCB, but we also have experience with ORMOCER, SU-8, and PI.
Si wafers are our main base material, but we have experience from laminate (PCB), Al, glass, quartz, flex (PI), LTCC, and are open to any other material, compatible with our processes in terms of mechanical and thermal properties.
Build-up
The figure below illustrates the build-up structure in a 4 layer MCM-D substrate:
CHIP ASSEMBLY TECHNOLOGIES
Wire bonding & Flip-Chip.
DESIGN RULES
General design considerations can be found in the EUROPRACTICE MCM SERVICE "Multichip Module Design Handbook"
Specific design rules: