Silicon analog to millimeter-wave technologies (SIAM)

The mm-wave marketf segment has historically been held by III-V semiconductor technologies. This market has remained somewhat of a niche market due to the high manufacturing cost, high power consumption, and limited integration scale of III-V semiconductor technologies. This situation is changing rapidly however, with silicon now being considered a realistic semiconductor material alternative to address these applications.

(Image: 2-26GHz 3 Stage LNA in 65nm SOI CMOS)

A change explained by the dramatic performance increase of active silicon devices (both SiGeC bipolar transistors and nano-scale CMOS devices) achieving cut-off frequencies far greater than 200GHz. However, there are still a number of open questions and unsolved problems considering the realization of key circuit building blocks for the next generation of high frequency communication systems, in particular, the choice and availability of a suitable and sufficiently powerful microelectronic technology, and on the early collaboration between design teams and chip manufacturers.

The SIAM project aims at the establishment of silicon technology platforms for emerging high frequency and mm-wave consumer applications like 77GHz automotive radar systems, 60GHz wireless networking and 100Gbit/s optical data communication systems. The project is divided into three work packages, each investigating the two advanced silicon technologies offered by ST microelectronics, 130nm SiGeC BiCMOS and 65nm CMOS-SOI on High Resistivity (HR) substrate. WP1 investigates the development of the silicon technologies and the realization of critical electronic components. WP2 investigates device characterization and modeling, necessary for technology development and optimization. WP3 investigates the design of critical mm-wave circuit blocks fabricated in the two technologies with circuit demonstrators designed to assess the suitability of these technologies for mm-wave consumer applications.

Acreo are involved in the project WP3.2 where the goal is to design components suitable for a 100 Gbit/s SCM fiber optic transceiver front end using ST’s 65nm CMOS technology on HR-SOI substrate. Together with the work that Ericsson and SP Devices perform, a complete 100 Gbit/s SCM fiber optic transceiver design is considered. The project performs 100 Gbit/s SCM sub-system simulations using the VSS simulation tool from AWR to establish the design requirements necessary for the components. Component designs and simulations are made using Cadence Virtuoso and Agilent RFDE environments together with the 65nm CMOS SOI design kit from ST. DRC and LVS are performed using Mentor Graphics Calibre.

The project has two tape outs, with the second tape out successfully completed in June 2010. A total of 18 circuits were submitted for manufacture. The circuits were recieved late 2010 so final measurements and reporting were completed as planned during Q211. Although the component specifications derived from system simulations are quite challenging, the measured results for the passive circuits (filters, baluns, combiners and phase shifters at 7 and 21GHz) and active circuits (2–40GHz single stage LNA, 2–26GHz 3 stage LNA, 2–26GHz RF combiner, 7 and 21GHz double balanced mixers and IQ modulators) are generally good, correlating well with simulations. These results indicate that the high performance offered by ST’s technology should meet the challenge, and, as such, the goals of the project are met.

Project summary:

Objective: To establish silicon technology platforms for emerging high frequency and mm-wave consumer applications.

Results (Acreo): 100 Gbit/s SCM fiber optic transceiver front end component design using ST’s 65nm CMOS technology on HR-SOI substrate including broadband mixers, LNAs, combiners, IQ modulators.

Project Duration: 3½ years, ending June 2011.

Project Sponsors: Eureka MEDEA+ program White Book 2 and VINNOVA.

Acreo contact: Duncan Platt, Tel. +46 (0)8 632 7854, e-mail: duncan.platt(at)acreo.se

Conference publications:

M. Salter, D. Platt, L. Pettersson, L. Aspemyr, M. Bao, ”Circuits and System Simulations for 100Gb/s optical SCM transmission”, 2009 IEEE International Conference on Electronic Circuits and Systems, Hammamet, Tunisia, Dec. 2009.

M. Salter, D. Platt, L. Pettersson, L. Aspemyr, M. Bao, ”65nm CMOS SOI Circuit Design for a 100Gb/s Optical SCM Transceiver”, Gigahertz Symposium, Lund, Sweden, Mar. 2010.

M. Salter, D. Platt, L. Pettersson, ”Broadband Mixer, LNA and Power Combiner in 65nm SOI CMOS”, Gigahertz Symposium, Lund, Sweden, Mar. 2010.

Project leader: ST Microelectronics, Crolles, France .

Project partners: ST Microelectronics (France), CEA-LETI (France), IEMN (France), IMS (France), Philips (Holland), Catena (Holland), TU Delft (Holland), Ericsson Research (Sweden), SP Devices (Sweden), Acreo (Sweden).